Silicon-based substrates which, for example, include a silicon carbide layer, are increasingly being used in standard components. For example, power semiconductors, which block voltages of up to more than 1.2 kV, are implemented using such substrates, as metal-oxide semiconductor transistors, for example, as trench metal-oxide semiconductor field-effect transistors (trench MOSFETs) or as trench bipolar transistors with an insulated gate electrode (trench IGBTs). Such power semiconductors are used, for example, in electric vehicle applications, i.e., motor vehicles with batteries, for example, lithium-ion cell-based batteries, or in photovoltaic systems. Micromechanical systems may also be implemented with such substrates. For micromechanical systems, the substrate may further include a silicon dioxide layer, a silicon nitride layer, or a silicon layer on which the silicon carbide layer is deposited.
To implement a trench MOSFET, for example, a substrate (monocrystalline n-doped 4H—SiC substrate) is used, whose silicon carbide layer has a hexagonal crystal structure and is n-doped. An n-doped silicon carbide buffer layer is arranged between the silicon carbide layer and a weakly n-doped silicon carbide drift zone (n-drift zone).
A (moderately) p-doped silicon carbide layer (p− layer) is arranged on the n-doped 4H—SiC substrate, which may be epitaxially grown or implanted. A more highly n-doped silicon carbide layer (n+ source), which may be epitaxially grown or implanted, is arranged on a portion of the p− layer, and acts as a source terminal. In this case, a rear side of the 4H—SiC substrate acts as a drain terminal. Next to the n+ source, a p+ terminal (p+ plug) is implanted into the p− layer, so that an upper side of the p+ plug interfaces with the upper side of the n+ source, and the p+ plug may be used for defining the channel potential. The p− layer and the n+ source are each structured via a recess which is arranged above a structure (trench) via which the n-drift zone is structured.
After the structuring, the trench may be coated with a gate oxide. Alternatively or additionally, a highly doped implantation may take place in the floor of the trench. A polysilicon gate is then deposited into the trench. Thus, a vertical channel region is created in the p− layer. This allows a higher packing density of parallel-connected transistors than with transistors having a lateral channel region.